Test circuit device for semiconductor memory apparatus

ABSTRACT

A test circuit device for a semiconductor memory device includes a main word line driving unit that generates a signal that swings between a driving voltage and one of a first voltage and a second voltage in response to a main decoding signal and a test mode signal, a local driving unit that generates a signal that swings between the driving voltage and one of the first voltage and the second voltage in response to a local decoding signal and the test mode signal, a driving voltage supplying unit that receives an output of the local driving unit and the test mode signal to supply a voltage that swings between the driving voltage and the first voltage, and a sub-word line driver that receives an output of the main word line driving unit and an output of the driving voltage supplying unit to determine whether the sub-word line is enabled or not.

The present application claims priority under 35 U.S.C. § 119(a) toKorean application number 10-2008-0052697, filed on Jun. 4, 2008, in theKorean Intellectual Property Office, which is incorporated herein byreference in its entirety as if set forth in full.

BACKGROUND

1. Technical Field

The embodiments described herein relate to a design of a semiconductormemory apparatus, and in particular, to a test circuit device for asemiconductor memory apparatus.

2. Related Art

As the capacity of semiconductor memory devices increases, the totalnumber of individual memory cells within a given area of thesemiconductor memory apparatus increases. Accordingly, the probabilityof a micro-bridge being established between adjacent word lines WL andbit lines BL increases.

FIG. 1 is a schematic circuit diagram of a conventional micro-bridgedetection circuit of a semiconductor memory apparatus. In FIG. 1, amicro-bridge detection circuit 11 of a semiconductor memory apparatusincludes a main word line driver 10, a local driver 20, a drivingvoltage supplying unit 30, and a sub word line driver 40.

The main word line driver 10 includes a first inverter circuit 11 thatreceives a main decoding signal ‘MDEC’ to supply a signal that swingsbetween a driving voltage VPP and a ground voltage VSS to the sub-wordline driver 40. The local driver 20 includes a second inverter 21 thatreceives a local decoding signal ‘LDEC’ to supply a signal that swingsbetween the driving voltage VPP and the ground voltage VSS to thedriving voltage supplying unit 30. The driving voltage supplying unit 30receives an output signal ‘LDB’ from the local driver 20 and a wordfloating test mode signal ‘TWLFLOAT’, and supplies the driving voltageVPP as an output signal ‘LD’ to the sub-word line driver 40. Thesub-word line driver 40 determines whether or not the sub-word line SWLis enabled in response to output signals ‘MWLB’, ‘LDB’, and ‘LD’ of themain word line driver 10, the local driver 20, and the driving voltagesupplying unit 30, respectively.

The unit arrangement of FIG. 1 is configured by a plurality of cellarrays in accordance with the configuration of the memory apparatus. Forpurposes of explanation, the cell array of FIG. 1 is added to assistwith describing operations of the micro-bridge detection circuit 1, anda minute bridge that is generated due to the presence of themicro-bridge between the word line and the bit line is schematicallyrepresented as a resistor MB.

FIG. 2 is a diagram representing conventional operation signals of acircuit according to the presence/absence of a micro-bridge. In FIGS. 1and 2, in a state where data “0” is stored in a memory cell of asemiconductor memory apparatus at an initial stage, when an activecommand signal ‘ACT’ is input, the main decoding signal ‘MDEC’ and thelocal decoding signal ‘LDEC’ are enabled at a high level. The firstinverter circuit 11 of the main word line driver 10, to which the maindecoding signal ‘MDEC’ is input, supplies an output signal ‘MWLB’ thatis enabled at a low level to the sub-word line 40. The second invertercircuit 21 of the local driver 20, to which the local decoding signal‘LDEC’ is input, supplies an output signal ‘LDB’ that is enabled at alow level to the driving voltage supplying unit 30. In this case, theword line floating test mode signal ‘TWLFLOAT’ is maintained to bedisabled at a low level. Thus, a PMOS transistor P2 that receives a lowword line floating test mode signal ‘TWLFLOAT’ is turned ON, and thedriving voltage supplying unit 30 that receives the output signal ‘LDB’of the local driver, which is enabled at a low level, supplies thedriving voltage VPP to the sub-word line driver 40.

The sub-word line driver 40 causes the sub-word line SWL to be enabledin response to the output signal ‘MWLB’ of the main word line driver 10that is enabled at a low level and the output signal ‘LDB’ of thedriving voltage supplying unit 30. When the sub-word line SWL isenabled, a bit line and a bit (bar) BL line are amplified by a bit linesense amplifier. In addition, after the charge sharing operation, data“0” is stored in the memory cell node. In this case, if the word linefloating test mode signal ‘TWLFLOAT’ is enabled at a high level, thenthe PMOS transistor P2 of the driving voltage supplying unit 30 thatreceives the word line floating test mode signal ‘TWLFLOAT’ through agate terminal is turned OFF. Thus, the driving voltage VPP that issupplied to the sub-word line driver 40 is intercepted and the sub-wordline SWL is in a floating state. If the floating state is maintained fora long time period, the micro-bridge MB is generated between thesub-word line and the bit line so that the level of the sub-word lineSWL is reduced to the ground voltage VSS level. Specifically, a currentpath is generated from the sub-word line SWL to the bit line so that thelevel of the sub-word line SWL is reduced to the ground voltage VSSlevel.

In the floating state, if data “1” is intended to be written into amemory cell by a write command, then the data “1” is transmitted to thebit line. However, since the level of the sub-word line SWL is reducedto the ground voltage level VSS, the memory cell node cannot store thedata “1”, and instead holds data “0”. After completing the writeoperation, if the precharge command PCG is performed, then the word linefloating test mode signal ‘TWLFLOAT’ is disabled. Next, when the activecommand is input again, the memory cell fails to read the data “1”, andthus, indicates that the micro-bridge MB is present. In contrast, if themicro-bridge MB is not present, then the sub-word line SWL is maintainedat the driving voltage VPP level. Thus, the data “1” can be successfullystored in the memory cell.

However, although the first, second, and third NMOS transistors N1, N2,and N3 are turned OFF when the sub-word line SWL is enabled, a leakagecurrent exists due to the characteristics of the first, second, andthird NMOS transistors N1, N2, and N3 in the turned OFF state. Thus,even when the micro-bridge MB is not present, the level of the sub-wordline SWL will be reduced to the ground voltage VSS level due to theleakage current. For example, since the leakage current caused by theNMOS transistors N1, N2, and N3 causes the level of the sub-word lineSWL to be reduced to the ground voltage level VSS, even in a normalstate when the micro-bridge MB is not present, it may be recognized thatthe micro-bridge MB is present, thereby making it difficult to exactlydetect the presence of the micro-bridge MB.

SUMMARY

A test circuit device for a semiconductor memory apparatus capable ofexactly detecting the presence of the micro-bridge is described herein.

In one aspect, test circuit device for a semiconductor memory apparatusincludes a main word line driving unit that generates a signal thatswings between a driving voltage and one of a first voltage and a secondvoltage in response to a main decoding signal and a test mode signal, alocal driving unit that generates a signal that swings between thedriving voltage and one of the first voltage and the second voltage inresponse to a local decoding signal and the test mode signal, a drivingvoltage supplying unit that receives an output of the local driving unitand the test mode signal to supply a voltage that swings between thedriving voltage and the first voltage, and a sub-word line driver thatreceives an output of the main word line driving unit and an output ofthe driving voltage supplying unit to determine whether the sub-wordline is enabled or not.

In other aspects, test circuit device of a semiconductor memoryapparatus includes a main word line driving unit that generates a signalthat swings between a driving voltage and one of a first voltage and asecond voltage in response to a main decoding signal and a test modesignal, a first low voltage controlling unit that supplies the secondvoltage to the main word line driving unit in response to the test modesignal, a local driving unit that generates a signal that swings betweenthe driving voltage and one of the first voltage and the second voltagein response to a local decoding signal and the test mode signal, asecond low voltage controlling unit that supplies the second voltage tothe local driving unit in response to the test mode signal, a drivingvoltage supplying unit that receives an output of the local driving unitand the test mode signal to supply a voltage that swings between thedriving voltage and the first voltage; and a sub-word line driver thatreceives an output of the main word line driving unit and an output ofthe driving voltage supplying unit to determine whether the sub-wordline is enabled or not.

These and other features, aspects, and embodiments are described belowin the section “Detailed Description.”

BRIEF DESCRIPTION OF THE DRAWINGS

Features, aspects, and embodiments are described in conjunction with theattached drawings, in which:

FIG. 1 is a schematic circuit diagram of a conventional micro-bridgedetection circuit of a semiconductor memory apparatus;

FIG. 2 is a diagram representing conventional operation signals of acircuit according to the presence/absence of a micro-bridge;

FIG. 3 is a schematic circuit diagram of an exemplary test circuitdevice of a semiconductor memory apparatus according to one embodiment.

FIG. 4 is a schematic circuit diagram of an exemplary test circuitdevice of a semiconductor memory apparatus according to otherembodiment.

DETAILED DESCRIPTION

FIG. 3 is a schematic circuit diagram of an exemplary test circuitdevice for a semiconductor memory apparatus according to one embodiment.In FIG. 3, a test circuit device 1 for a semiconductor memory apparatuscan be configured to include a main word line driving unit 100, a localdriving unit 200, a driving voltage supplying unit 30, and a sub-wordline driver 40.

The main word line driving unit 100 can output a signal that swingsbetween a high voltage and a low voltage in response to a main decodingsignal ‘MDEC’ and a test mode signal ‘TWLFLOAT’ to supply an outputsignal ‘MWLB’ to the sub-word line driver 40. Here, for example, thehigh voltage may serve as a driving voltage VPP and the low voltage mayserve as a first voltage or a second voltage. When the main decodingsignal ‘MDEC’ is enabled, according to whether the test mode signal‘TWLFLOAT’ is enabled or not, the main word line driving unit 100 cansupply the first voltage or the second voltage to the sub-word linedriver 40. In addition, when the main decoding signal ‘MDEC’ isdisabled, the driving voltage VPP can be supplied to the sub-word linedriver 40. Accordingly, for example, the first voltage can be the groundvoltage VSS and the second voltage can be a negative bias voltage VNBthat is lower than the ground voltage VSS. Hereinafter, for purposes ofexplanation, the first voltage refers to the ground voltage VSS, and thesecond voltage refers to the negative bias voltage VNB.

If the test mode signal ‘TWLFLOAT’ is enabled, then the main word linedriving unit 100 can supply the second voltage, i.e., the negative biasvoltage VNB, as a low voltage. Accordingly, it is possible to reduce theOFF leakage current of the NMOS transistors of the test circuit device1. Accordingly, with the reduction of the OFF leakage current, themicro-bridge MB present between the bit line and the word line can beprecisely detected.

The local driving unit 200 can provide an output signal ‘LDB’ to thedriving voltage supplying unit 30 that swings between the high voltageand the low voltage in response to the local decoding signal ‘LDEC’ andthe test mode signal ‘TWLFLOAT’. For example, the high voltage can bethe driving voltage VPP and the low voltage can be the first voltage VSSor the second voltage VNB. When the local decoding signal ‘LDEC’ isenabled, according to whether the test mode signal ‘TWLFLOAT’ is enabledor not, the local driving unit 200 can supply the first voltage VSS orthe second voltage VNB to the driving voltage supplying unit 30 as theoutput signal ‘LDB’. In addition, when the local decoding signal ‘LDEC’is disabled, the driving voltage VPP can be supplied to the drivingvoltage supplying unit 30. If the test mode signal ‘TWLFLOAT’ isenabled, then the local driving unit 200 can supply the second voltage,i.e., the negative bias voltage VNB, as a low voltage. Accordingly, itis possible to reduce the OFF leakage current of the NMOS transistorthat configures the test circuit device 1. Thus, if the OFF leakagecurrent is reduced, then the micro-bridge MB present between the bitline and the word line can be precisely detected.

The driving voltage supplying unit 30 can supply a voltage that swingsbetween the driving voltage VPP and the first voltage VSS in response tothe output of the local driving unit 200 and the test mode signal‘TWLFLOAT’. When the local decoding signal ‘LDEC’ is disabled, thedriving voltage supplying unit 30 can supply the first voltage VSS tothe sub-word line driver 40. If the sub-word line SWL is enabled andthen the test mode signal ‘TWLFLOAT’ is enabled, then the drivingvoltage supplying unit 30 can prevent the driving voltage VPP from beingsupplied to the sub-word line driver 40 to place the enabled sub-wordline SWL in a floating state. Here, the sub-word line SWL can be in thefloating state to detect the current leakage due to the micro-bridge MB.

The sub-word line driver 40 causes the sub-word line SWL to be enabledin response to the output signal ‘MWLB’ of the main word line drivingunit 100.

In FIG. 3, the main word line driving unit 100 can include a firstsignal selector 110 receiving the main decoding signal ‘MDEC’ as aninput, and a first low voltage supplying unit 120 that supplies thefirst voltage VSS or the second voltage VNB to the first signal selector110 according to whether the test mode signal ‘TWLFLOAT’ is enabled ornot. When the main decoding signal ‘MDEC’ is disabled, the first signalselector 110 can supply the driving voltage VPP to the sub-word linedriver 40 as the output signal ‘MWLB’. When the main decoding signal‘MDEC’ is enabled, the first signal selector 110 can supply the firstvoltage VSS or the second voltage VNB to the sub-word line driver 40 asthe output signal “MWLB’.

The first low voltage supplying unit 120 can supply the first or secondvoltage VSS or VNB to the first signal selector 110 in response to thetest mode signal ‘TWLFLOAT’. The first low voltage supplying unit 120can supply the second voltage VNB to the first signal selector 110 whenthe test mode signal ‘TWLFLOAT’ is enabled, and can supply the firstvoltage VSS to the first signal selector 110 when the test mode signal‘TWLFLOAT’ is disabled.

The first signal selector 110 can be configured to include a first PMOStransistor P1, wherein the main decoding signal ‘MDEC’ can be suppliedthrough a gate terminal and the driving voltage VPP can be suppliedthrough a source terminal, and a first NMOS transistor N1, wherein themain decoding signal ‘MDEC’ can be supplied through a gate terminal, asource terminal can be connected to a first node A, and a drain terminalcan be connected to a drain terminal of the first PMOS transistor P1.

The first low voltage supplying unit 120 can include a fifth NMOStransistor N5, wherein the test mode signal ‘TWLFLOAT’ can be suppliedthrough a gate terminal, the second voltage VNB can be supplied througha source terminal, and a drain terminal can be connected to the firstnode A, and a sixth NMOS transistor N6, wherein an inverted test modesignal ‘TWLFLOATB’ can be supplied through a gate terminal, the firstvoltage VSS can be supplied through a source terminal, and a drainterminal can be connected to the first node A.

The local driving unit 200 can include a second signal selector 210 thatcan receive the local decoding signal ‘LDEC’ as an input, and a secondlow voltage supplying unit 220 that can supply the first voltage VSS orthe second voltage VNB to the second signal selector 210 according towhether the test mode signal ‘TWLFLOAT’ is enabled or not. When thelocal decoding signal ‘LDEC’ is disabled, the second signal selector 210can supply the driving voltage VPP to the driving voltage supplying unit30 as the output signal ‘LDB’. When the local decoding signal ‘LDEC’ isenabled, the second signal selector 210 can supply the first voltage VSSor the second voltage VNB to the driving voltage supplying unit 30 asthe output signal ‘LDB’.

The second low voltage supplying unit 220 can supply the first voltageVSS or the second voltage VNB to the second signal selector 210 inresponse to the test mode signal ‘TWLFLOAT’. The second low voltagesupplying unit 220 can supply the second voltage VNB to the secondsignal selector 210 when the test mode signal ‘TWLFLOAT’ is enabled, andcan supply the first voltage VSS to the second signal selector 210 whenthe test mode signal ‘TWLFLOAT’ is disabled.

The second signal selector 210 can include a second PMOS transistor P2,wherein the local decoding signal ‘LDEC’ can be supplied through a gateterminal and the driving voltage VPP can be supplied through a sourceterminal, and a second NMOS transistor N2, wherein the local decodingsignal ‘LDEC’ can be supplied through a gate terminal, a source terminalcan be connected to a second node B, and a drain terminal can beconnected to a drain terminal of the second PMOS transistor P2.

The second low voltage supplying unit 220 can include a seventh NMOStransistor N7, wherein the test mode signal ‘TWLFLOAT’ can be suppliedthrough a gate terminal and a drain terminal can be connected to thesecond node B, and an eighth NMOS transistor N8, wherein an invertedtest mode signal ‘TWLFLOATB’ can be supplied through a gate terminal anda drain terminal can be connected to the second node B.

The driving voltage supplying unit 30 can include a detector 32 that canreceive the test mode signal ‘TWLFLOAT’, and a voltage selector 31 thatcan receive the output signal ‘LDB’ of the local driving unit 200. Thedetector 32 can determine whether to supply the driving voltage VPP tothe voltage selector 31 in response to the test mode signal ‘TWLFLOAT’.For example, if the test mode signal ‘TWLFLOAT’ is enabled, then thedetector 32 can not supply the driving voltage VPP to the voltageselector 31. Conversely, if the test mode signal ‘TWLFLOAT’ is disabled,then the detector 32 can supply the driving voltage VPP to the voltageselector 31. Therefore, when the test mode signal ‘TWLFLOAT’ is enabled,the driving voltage VPP is not supplied to the sub-word line driver 40as the output signal ‘LD’, thereby detecting the micro-bridge MB due tothe floating state of the sub-word line SWL.

The detector 32 can include a fifth PMOS transistor P5, wherein the testmode signal ‘TWLFLOAT’ can be supplied through a gate terminal and thedriving voltage VPP can be supplied through a source terminal.

The voltage selector 31 can include a third PMOS transistor P3, whereinthe output signal ‘LDB’ of the local driving unit 200 can be suppliedthrough a gate terminal and a source terminal can be connected to thedrain terminal of the fifth PMOS transistor P5, and a third NMOStransistor N3, wherein the output signal LDB of the local driver 40 canbe supplied through a gate terminal, the first voltage VSS can besupplied through a source terminal, and a drain terminal can beconnected to a drain terminal of the third PMOS transistor P3.

The sub-word line driver 40 can include a third signal selector 41 thatreceives the output signal ‘MWLB’ of the main word line driving unit 100and a signal supplying unit 42 that can receive the output signal ‘LDB’of the local driving unit 200. The third signal selector 41 can supply asignal, i.e., the output signal ‘LD’, that swings between a voltagesupplied from the driving voltage supplying unit 30 and the firstvoltage VSS to the sub-word line SWL in response to the output signal‘MWLB’ of the main word line driving unit 100. The signal supplying unit42 can determine whether to produce the output of the third signalselector 41 to the sub-word line SWL in response to the output signal‘LDB’ of the local driving unit 200.

The third signal selector 41 can include a fourth PMOS transistor P4,wherein the output signal ‘MWLB’ of the main word line driving unit 100can be supplied through a gate terminal, the output signal ‘LD’ of thedriving voltage supplying unit 30 can be supplied through a sourceterminal, and a drain terminal can be connected to a third node C, and afourth NMOS transistor N4, wherein the output signal ‘MWLB’ of the mainword line driving unit 100 can be supplied through a gate terminal, thefirst voltage VSS can be supplied through a source terminal, and a drainterminal can be connected to the third node C.

The signal supplying unit 42 can include a ninth NMOS transistor N9,wherein the output signal ‘LDB’ of the local driving unit 200 can besupplied through a gate terminal and a drain terminal can be connectedto the third node C. Here, the sub-word line driver 40 can supply asub-word line enable signal ‘SWL_EN’ to the sub-word line SWL throughthe third node C.

An exemplary operation of a test circuit device for a semiconductormemory apparatus 1 will be described with reference to FIGS. 2 and 3.

In a state where data “0” is stored in a memory cell of a semiconductormemory device at an initial stage, when an active command signal ‘ACT’is input, the main decoding signal ‘MDEC’ and the local decoding signal‘LDEC’ can be enabled at a high level. In this case, the disabled stateof the test mode signal ‘TWLFLOAT’ can be maintained. Since the testmode signal ‘TWLFLOAT’ is disabled, the fifth NMOS transistor N5 of thefirst low voltage supplying unit 120 of the main word line driving unit100 can be turned OFF, and the sixth NMOS transistor N6 can be turnedON. Accordingly, the first voltage VSS can be supplied to the firstsignal selector 110. If the main decoding signal ‘MDEC’ is enabled at ahigh level, then the first PMOS transistor P1 of the first signalselector 110 can be turned OFF and the first NMOS transistor N1 can beturned ON. Accordingly, the first voltage VSS can be supplied to thesub-word line driver 40 through the first NMOS transistor N1 that isturned ON.

Since the test mode signal ‘TWLFLOAT’ is disabled, the seventh NMOStransistor N7 of the second low voltage supplying unit 220 of the localdriving unit 200 can be turned OFF, and the eighth NMOS transistor N8can be turned ON. Accordingly, the first voltage VSS can be supplied tothe second signal selector 210. If the local decoding signal ‘LDEC’ isenabled at a high level, then the second PMOS transistor P2 of thesecond signal selector 210 can be turned OFF and the second NMOStransistor N2 can be turned ON. Thus, the first voltage VSS can besupplied to the driving voltage supplying unit 30 through the secondNMOS transistor N2 that is turned ON.

In addition, since the driving voltage supplying unit 30 can receive theoutput signal ‘LDB’, which can be enabled at a low level through thelocal driving unit 200, the PMOS transistor P3 of the voltage selector31 of the driving voltage supplying unit 30 can be turned ON, and thethird NMOS transistor N3 can be turned OFF. Furthermore, since the testmode signal ‘TWLFLOAT’ can be disabled, the fifth PMOS transistor P5 ofthe detector 32 can be turned ON and the driving voltage VPP can besupplied to the sub-word line driver 40 through the fifth PMOStransistor P5 and the third PMOS transistor P3.

The sub-word line driver 40 can receive the output signal ‘MWLB’ of themain word line driving unit 100, which can be enabled at a low level.Accordingly, the fourth PMOS transistor P4 of the third signal selector41 of the sub-word line driver 40 can be turned ON, and the fourth NMOStransistor N4 can be turned OFF. In addition, the ninth NMOS transistorN9 that receives the output signal ‘LDB’ of the local driving unit 200enabled at a low level can be turned OFF. The driving voltage VPP thatis supplied from the driving voltage supplying unit 30 through theturned ON fourth PMOS transistor P4 can be supplied as the sub-word lineenable signal ‘SWL_EN’. Here, the sub-word line enable signal ‘SWL_EN’that is enabled at a high level by the driving voltage VPP can cause thesub-word line SWL to be enabled at the same level as the driving voltageVPP.

If the sub-word line SWL is enabled, then a bit line BL and a bit (bar)line BL can be amplified by a bit line sense amplifier. Accordingly,after the charge sharing operation, the data “0” can be stored in thememory cell node again. Then, in order to detect the micro-bridge MB,the test mode signal ‘TWLFLOAT’ can be enabled at a high level. If thetest mode signal ‘TWLFLOAT’ is enabled at a high level, then the fifthPMOS transistor P5 of the detector 32 can be turned OFF, and the drivingvoltage VPP that is supplied to the sub-word line SWL can beintercepted. Accordingly, the enabled sub-word line SWL can be in afloating state. If the floating state of the sub-word line SWL ismaintained for a long time period, the sub-word line SWL can becomedisabled or can be maintained in the enabled state, according to thepresence of the micro-bridge MB between the word line and the bit line.Thus, if the micro-bridge MB is present, the current path can begenerated, thereby decreasing the level of the sub-word line SWL to aground voltage VSS level.

When the sub-word line SWL is enabled, the third NMOS transistor N3 ofthe voltage selector 31, the fourth NMOS transistor N4 of the thirdvoltage selector 41, and the ninth NMOS transistor N9 of the signalsupplying unit 42 can all be turned OFF. However, the OFF leakagecurrent exists due to the characteristics of the NMOS transistors. Evenwhen the micro-bridge MB is not present, the level of the sub-word lineSWL may be reduced to the ground voltage VSS level. Thus, if the testmode signal ‘TWLFLOAT’ is enabled at a high level, then the first lowvoltage supplying unit 120 and the second low voltage supplying unit 220can supply the second voltage VNB to the first signal selector 110 andthe second signal selector 210, instead of the first voltage VSS. Forexample, when the test mode signal ‘TWLFLOAT’ is enabled, the sixth NMOStransistor N6 of the first low voltage supplying unit 120 can be turnedOFF and the fifth NMOS transistor N5 can be turned ON. Thus, the secondvoltage VNB can be supplied to the source terminal of the first NMOStransistor N1 of the first signal selector 110. Similarly, the eighthNMOS transistor N8 of the first signal selector 110 can be turned OFF,and the seventh NMOS transistor N7 can be turned ON to supply the secondvoltage VNB to the source terminal of the second NMOS transistor N2 ofthe second signal selector instead of the first voltage VSS.

By supplying the second voltage VNB to the source terminals of the firstand second NMOS transistors N1 and N2, instead of the first voltage VSS,the fourth NMOS transistor N4 of the third signal selector that receivesthe output signal ‘MWLB’ of the first signal selector through the gateterminal, the third NMOS transistor N3 of the voltage selector 31 thatreceives the output signal ‘LDB’ of the second signal selector throughthe gate terminal, and the ninth NMOS transistor N9 of the signalsupplying unit 42 can all be turned OFF quickly. Thus, the OFF leakagecurrent from the NMOS transistors N3, N4, and N9 can be significantlyreduced.

If the data “1” is written into a memory cell by a write operation andthe precharge operation PCG is performed, then the test mode signal‘TWLFLOAT’ can be disabled. If the micro-bridge MB is not present, thenthe sub-word line SWL can be maintained at the driving voltage VPPlevel. Thus, when the active command signal ACT is input again, the data“1” can be read from the memory cell node. In contrast, if the data “1”cannot be read from the memory cell node, then the micro-bridge MB canbe exactly detected.

According to the one embodiment, in order to detect the micro-bridge MB,when the test mode signal is enabled, the leakage current prevent unitcan supply the negative bias voltage to rapidly reduce the OFF leakagecurrent of the NMOS transistors, thereby making it possible to detectwhen the level of the sub-word line is reduced due to the presence ofthe micro-bridge.

FIG. 4 is a schematic circuit diagram of another exemplary test circuitdevice for a semiconductor memory apparatus according to one embodiment.In FIG. 4, a test circuit device 2 for a semiconductor memory apparatuscan be configured to include a main word line driving unit 1100, a firstlow voltage controlling unit 1200, a local driving unit 2100, a secondlow voltage controlling unit 2200, a driving voltage supplying unit 30,and a sub-word line driver 40.

In FIG. 4, the main word line driving unit 1100 can be configured to asignal that swings between the driving voltage VPP and one of the firstvoltage VSS and the second voltage VNB in response to the main decodingsignal MDEC and the test mode signal TWLFLOAT. The first low voltagecontrolling unit 1200 can be configured to supply the second voltage1200 to the main word line driving unit 1100 in response to the testmode signal TWLFLOAT.

The local driving unit 2100 can be configured to generate a signal thatswings between the driving voltage VPP and one of the first voltage VSSand the second voltage VNB in response to a local decoding signal LDECand the test mode signal TWLFLOAT. The second low voltage controllingunit 2200 that supplies the second voltage VNB to the local driving unit2100 in response to the test mode signal TWLFLOAT.

In FIG. 4, the main word line driving unit 1100 can be configured toinclude a first PMOS transistor P1, a first and a sixth NMOS transistorsN1 and N6, and the first low voltage controlling unit 1200 can beconfigured to include a fifth NMOS transistor N5. The local driving unit2100 can be configured to include a second PMOS transistor P2, a secondand a eighth NMOS transistors N2 and N8, and the second low voltagecontrolling unit 2200 can be configured to include a seventh NMOStransistor N7.

While certain embodiments have been described above, it will beunderstood that the embodiments described are by way of example only.Accordingly, the device and method described herein should not belimited based on the described embodiments. Rather, the devices andmethods described herein should only be limited in light of the claimsthat follow when taken in conjunction with the above description andaccompanying drawings.

1. A test circuit device for a semiconductor memory apparatus, comprising: a main word line driving unit that generates a signal that swings between a driving voltage and one of a first voltage and a second voltage in response to a main decoding signal and a test mode signal; a local driving unit that generates a signal that swings between the driving voltage and one of the first voltage and the second voltage in response to a local decoding signal and the test mode signal; a driving voltage supplying unit that receives an output of the local driving unit and the test mode signal to supply a voltage that swings between the driving voltage and the first voltage; and a sub-word line driver that receives an output of the main word line driving unit and an output of the driving voltage supplying unit to determine whether the sub-word line is enabled or not.
 2. The test circuit device of claim 1, wherein the main word line driving unit includes: a first signal selector that supplies a signal that swings between the driving voltage and the one of the first voltage and the second voltage in response to the main decoding signal; and a first low voltage supplying unit that supplies one of the first voltage and the second voltage to the first signal selector in response to the test mode signal.
 3. The test circuit device of claim 2, wherein the first low voltage supplying unit supplies the second voltage to the first signal selector when the test mode signal is enabled, and supplies the first voltage to the first signal selector when the test mode signal is disabled.
 4. The test circuit device of claim 2, wherein the first low voltage supplying unit includes: a first NMOS transistor having a gate terminal receiving the test mode signal, a source terminal receiving the second voltage, and a drain terminal connected to a first node; and a second NMOS transistor having a gate terminal receiving an inverted test mode signal, a source terminal receiving the first signal, and a drain terminal connected to the first node, wherein one of the first voltage and the second voltage is supplied to the first signal selector through the first node.
 5. The test circuit device of claim 1, wherein the local driving unit includes: a second signal selector that supplies a signal that swings between the driving voltage and one of the first voltage and the second voltage in response to the local decoding signal; and a second low voltage supplying unit that supplies one of the first voltage and the second voltage to the second signal selector in response to the test mode signal.
 6. The test circuit device of claim 5, wherein the second low voltage supplying unit supplies the second voltage to the second signal selector when the test mode signal is enabled, and supplies the first voltage to the second signal selector when the test mode signal is disabled.
 7. The test circuit device of claim 5, wherein the second low voltage supplying unit includes: a third NMOS transistor having a gate terminal receiving the test mode signal, a source terminal receiving the second voltage, and a drain terminal connected to a second node; and a fourth NMOS transistor having a gate terminal receiving the inverted test mode signal, a source terminal receiving the first signal, and a drain terminal connected to the second node, wherein one of the first voltage and the second voltage is supplied to the second signal selector through the second node.
 8. The test circuit device of claim 1, wherein the driving voltage supplying unit includes: a voltage selector that supplies the voltage that swings between the driving voltage and the first voltage in response to the output of the local driving unit; and a detector that determines to supply the driving voltage to the voltage selector in response to the test mode signal.
 9. The test circuit device of claim 8, wherein the detector does not supply the driving voltage to the voltage selector when the test mode signal is enabled, and supplies the driving voltage to the signal selector when the test mode signal is disabled.
 10. The test circuit device of claim 1, wherein the first voltage includes a ground voltage.
 11. The test circuit device of claim 1, wherein the second voltage includes a negative bias voltage that is lower than the ground voltage.
 12. The test circuit device of claim 1, wherein the sub-word line driver includes: a third signal selector that outputs a signal that swings between the output of the driving voltage supplying unit and the first voltage in response to the output of the main word line driving unit; and a signal supplying unit that supplies the output of the third signal selector to the sub-word line.
 13. A test circuit device for a semiconductor memory apparatus, comprising: a main word line driving unit that generates a signal that swings between a driving voltage and one of a first voltage and a second voltage in response to a main decoding signal and a test mode signal; a first low voltage controlling unit that supplies the second voltage to the main word line driving unit in response to the test mode signal; a local driving unit that generates a signal that swings between the driving voltage and one of the first voltage and the second voltage in response to a local decoding signal and the test mode signal; a second low voltage controlling unit that supplies the second voltage to the local driving unit in response to the test mode signal; a driving voltage supplying unit that receives an output of the local driving unit and the test mode signal to supply a voltage that swings between the driving voltage and the first voltage; and a sub-word line driver that receives an output of the main word line driving unit and an output of the driving voltage supplying unit to determine whether the sub-word line is enabled or not.
 14. The test circuit device of claim 13, wherein the main word line driving unit supplies the signal that swings between the driving voltage and the first voltage when the test mode signal is disabled, and supplies the signal that swings between the driving voltage and the second voltage when the test mode signal is enabled.
 15. The test circuit device of claim 14, wherein the first low voltage controlling unit supplies the second voltage to the main word line driving unit when the test mode signal is enabled.
 16. The test circuit device of claim 13, wherein the local driving unit supplies the signal that swings between the driving voltage and the first voltage when the test mode signal is disabled, and supplies the signal that swings between the driving voltage and the second voltage when the test mode signal is enabled.
 17. The test circuit device of claim 16, wherein the second low voltage controlling unit supplies the second voltage to the local driving unit when the test mode signal is enabled.
 18. The test circuit device of claim 13, wherein the driving voltage supplying unit includes: a voltage selector that supplies the voltage that swings between the driving voltage and the first voltage in response to the output of the local driving unit; and a detector that determines to supply the driving voltage to the voltage selector in response to the test mode signal.
 19. The test circuit device of claim 18, wherein the detector does not supply the driving voltage to the voltage selector when the test mode signal is enabled, and supplies the driving voltage to the signal selector when the test mode signal is disabled.
 20. The test circuit device of claim 13, wherein the first voltage includes a ground voltage.
 21. The test circuit device of claim 13, wherein the second voltage includes a negative bias voltage that is lower than the ground voltage.
 22. The test circuit device of claim 13, wherein the sub-word line driver includes: a signal selector that outputs a signal that swings between the output of the driving voltage supplying unit and the first voltage in response to the output of the main word line driving unit; and a signal supplying unit that supplies the output of the signal selector to the sub-word line. 